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Challenging the Best HEVC Fractional Pixel FPGA Interpolators with Reconfigurable and Multi-frequency Approximate Computing


Abstract


??Applicable in different fields and markets, low energy High Efficiency Video Coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this paper, a Field Programmable Gate Array (FPGA) implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy vs. quality trade-off to further reduce energy.

KeyWords
FIR filters, low power architectures, low power design, FPGA, embedded applications, signal processing, runtime reconfiguration, reconfigurable computing.



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