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Cache Coherence Scheme for HCS-Based CMP and Its System Reliability Analysis


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Abstract


In previous work, a new network switch architecture, hybrid circuit-switched (HCS) network, has been proposed and evaluated. In doing so, it has been studied for use in a multi-processor system, with a focus on power and throughput. However, cache coherence and its connection with chip reliability have not been fully studied previously for multi-processor systems. In this paper, we study this problem by discussing the implementation of cache coherence on an HCS-based chip multi-processor and present a way to model the reliability of these protocols based on fault tree analysis and two-terminal networking models. We focus our efforts on three cache coherence protocols: Write-Once, Modied, Exclusive, Shared, Invalid (MESI), and Modied, Owned, Exclusive, Shared, Invalid (MOESI), and obtain expressions for the reliability probabilities of the system. Our results show that theWrite-Once protocol is 14Percent less reliable than MOESI, while theMESI protocol is 2.5Percent less reliable thanMOESI. We also demonstrate that the reliability of these protocols is 40.22Percent and 59.83Percent better, on average, when implemented on an HCS network rather than an elastic buffer-based network or a bus-based network, respectively.

KeyWords
Cache coherence, networking switch, system reliability, fault tree analysis (FTA), 2-terminal model



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