FPGA Implementation of Stepping Correlation Acquisition Algorithm for Beidou II B1 Signal
This paper based on the time domain serial acquisition principle, a multi-channel step correlation acquisition algorithm is designed and implemented by FPGA. According to the principle of modular design, the whole acquisition system is divided into local carrier NCO module, local code NCO module, and operation unit module. Their functions are to generate local in-phase and quadrature carriers, generate local pseudo code, and down-conversion of intermediate frequency signal, then carry out related cumulative calculation, and finally rerunning threshold judgment. Every module is implemented in Quartus, and the function simulation is achieved in Modelsim. Through the simulation of the real time Beidou satellite digital IF signal in the whole acquisition module, and compared with the Matlab simulation results based on FFT parallel code phase acquisition, The results show that the algorithm can correctly and effectively capture the Beidou satellite signals it can improve the acquisition efficiency and reduce the utilization ratio of resources.
Beidou satellite acquisition, baseband signal, step correlation, FPGA