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An FPGA-based Hardware Emulator for Neuromorphic Chip with RRAM


3D Reconstruction in Canonical
Abstract


Neuromorphic chip with RRAM devices has been demonstrated as a promising computing platform for neural network-based applications. By directly mapping the weight matrices of neural networks onto RRAM-based crossbar arrays, high energy and area efficiency can be achieved. However, the design of an RRAM-based neuromorphic chip faces many constraints due to the variability and limitations of RRAM. Simulation and emulation can help in the design of a neuromorphic chip prior to fabrication. However, software-based chip simulation on CPU is slow, especially for large-scale NoC based chip design. In this paper, we present a hardware emulator on FPGA for an RRAM-based neuromorphic chip. Our emulator supports the emulation of static and dynamic variation of the RRAMbased crossbars used in the neural cores of a neuromorphic chip. Furthermore, a Network-on-Chip (NoC) is also implemented on FPGA to emulate the communication between the neural cores. Using the emulator, we show that effects such as RRAM write and read noise, and stuck-at faults affect the accuracy of an application on a neuromorphic chip. We also demonstrate the utility of the emulator in investigating NoC topologies, routing buffer depths, and neural core mappings.

KeyWords
Neuromorphic computing, RRAM, spiking neural network, FPGA emulation.



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