Hidden Fault Analysis of FPGA Projects for Critical Applications
This paper focuses on the problem of hidden faults, which is seen like a growth one inherent in modern safety-related systems. The special feature of these is the designing for operation in two modes: normal and emergency. Digital components can accumulate hidden failures over a long-term normal mode. This reduces their fault tolerance and functional safety of the system in the most responsible emergency mode. Two conditions for occurrence of the hidden fault problem as a growth one are considered in view of a resource approach, which in the development of models, methods and means highlights levels of replication and diversification. Safety-related systems are analyzed as computer systems that have increased to the level of diversification to address the security challenge. Their components are still stamped at a level of resource replication using matrix structures to process data in parallel codes. Faulttolerant solutions become fault-safe with a sufficient level of circuit checkability, which is commonly known as testability, i.e. structural checkability, depending only on the structure of the circuit. In the operating mode, the checkability becomes structurally-functional, and in critical applications it is converted into a dual-mode, the shortage of which causes the hidden fault problem. A method of analyzing circuits for the possibility of hidden faults is suggested. The method is illustrated on example of an iterative array multiplier implemented in an FPGA project with a LUT-oriented architecture. A program model for the resulting scheme has been developed and potentially dangerous points have been found in it in which the hidden fault problem of may manifest itself.
hidden fault, FPGA, LUT-oriented architecture, safety-related system, digital component, growth problem, resource approach, replication, diversification, matrix structure, checkability, iterative array multiplier, potentially dangerous points.