BE/BTech & ME/MTech Final Year Projects for Computer Science | Information Technology | ECE Engineer | IEEE Projects Topics, PHD Projects Reports, Ideas and Download | Sai Info Solution | Nashik |Pune |Mumbai
director@saiinfo settings_phone02536644344 settings_phone+919270574718 +919096813348 settings_phone+917447889268
logo


SAI INFO SOLUTION


Diploma | BE |B.Tech |ME | M.Tech |PHD

Project Development and Training

Search Project by Domainwise


High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters


3D Reconstruction in Canonical
Abstract


An extremely high-resolution, 2-D Vernier fieldprogrammable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is limited to less than 20 ns. To achieve both high-precision phase division and wide measurement range, a phase-locked loop (PLL)-based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this article. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For a concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6-ps resolution. The differential nonlinearity (DNL), integral nonlinearity (INL), and rms resolution are measured to be merely ??0.157 to 0.137 LSB, ??0.176 to 0.184 LSB, and 1.0 LSB, which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high-precision phase division technique can be applied to not only the TDC but also the digital-to-time converter (DTC) to enrich its future applications.

KeyWords
2-D Vernier, delay matrix, double data rate (DDR), overclocking, phase division, phase-locked loop (PLL), time-to-digital converter (TDC).



Share
Share via WhatsApp
BE/BTech & ME/MTech Final Year Projects for Computer Science | Information Technology | ECE Engineer | IEEE Projects Topics, PHD Projects Reports, Ideas and Download | Sai Info Solution | Nashik |Pune |Mumbai
Call us : 09096813348 / 02536644344
Mail ID : developer.saiinfo@gmail.com
Skype ID : saiinfosolutionnashik