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Design of Parallel Acceleration Method of Convolutional Neural Network Based on FPGA


Scalable and Secure Big Data I

3D Reconstruction in Canonical
Abstract


In the current FPGA implementation of convolution acceleration, convolution parallelism is limited by on-chip resources and data throughput. A general parallel convolution acceleration unit design is proposed to ensure the computing efficiency of the acceleration circuit and each layer. The calculation and quantization methods are optimized, and the results of weights and feature maps are stored using semifloating points, and the convolution process is performed using fixed-point calculations. The above strategy guarantees the use efficiency and calculation accuracy of DSPs. Using the proposed design method, a Lenet-5 convolutional neural network was deployed on the SOC development platform of ZCU102. At a working frequency of 150MHz, the computing performance of FPGA reached 28.8 GOPS, and the recognition rate reached 99.11% on the MNIST data level

KeyWords
convolution acceleration, FPGA, Lenet-5



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