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FPGA Implementation of Encryption Algorithms Based on Residual Polynomials


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Abstract


This paper describes an encryption algorithm based on a polynomial system of residual classes. We study the FPGA bitstream implementation on the Xilinx and 16-nm UltraScaleā?¢ ASIC architecture which enables floating-point operation, multi-processing, parallelism, pipelining, highperformance computing, etc. The software-based bitstream encryption and on-chip decryption are performed with the stored encryption key and encrypted bitstream, generated by a Vivado tool. The self-authenticating algorithms with a symmetric key are investigated. The encryption algorithms are implemented using the polynomial system of residual numbers. Data encryption in a residual number system is effectively implemented by ASICs. Design of irreducible polynomial is proposed and discussed. Our developments and findings are empowered by the low-power FinFET FPGA architecture.

KeyWords
cybersecurity, FPGA, encryption, non-positional number systems, cryptography, polynomial.



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