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Optimizing FPGA Logic Circuitry for Variable Voltage Supplies


3D Reconstruction in Canonical
Abstract


Unlike central processing units (CPUs), fieldprogrammable gate arrays (FPGAs) have conventionally been powered with a fixed supply voltage (Vdd). However, recent efforts have shown that adopting dynamic voltage scaling reduces FPGA power consumption significantly. In this article, we analyze the delay sensitivity of different FPGA circuit elements to supply voltage changes and determine that conventional lookup table (LUT) designs greatly impact variable Vdd operation. To build FPGAs with lower delay sensitivity to Vdd, we propose several new LUT designs, including gate boosting the LUT, decoding the slowest two inputs of the LUT, and using separate voltage islands for the FPGA LUTs and routing. Our fastest proposed design (decodedriver island) reduces the area-delay product of the FPGA logic plus routing tile compared to a conventional design by 12% and 52% at Vdd values of 0.8 V (the nominal voltage) and 0.6 V, respectively. Since our proposed FPGA tile designs are faster and have lower delay sensitivity to voltage, they offer better Energy-Delay2 product (ED2) than that of the baseline at nominal Vdd and below. Our decode-driver-island FPGA achieves a 26% ED2 reduction over the conventional design at the most efficient ED2 operating point.

KeyWords
Dynamic voltage scaling (DVS), field programmable gate arrays (FPGAs).



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