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FPGA BASED HARDWARE DESIGN OF PCA FOR FACE RECOGNITION


3D Reconstruction in Canonical
Abstract


This work mainly focuses on the hardware implementation of the modules required for Principal Component analysis (PCA) algorithm, which is the most popular liner-unsupervised dimensionality reduction algorithm. The PCA algorithm has been used to reduce the dimensionality of the database, where several face images have been stored for face recognition purpose. Also, it has been used to find the total number of eigen-faces that should be used to retain a certain amount of variance in the dataset. These eigen-faces have been used later to determine, whether a new input face image can be recognized or not. The high-level synthesis has been done in Vivado HLS using the device xcvu11p-flga2577-1-e. The purpose behind this work is to make the PCA technique available as a portable device for face recognition in real time applications such as identification of criminals.

KeyWords
Principal Component Analysis (PCA), Singular Value Decomposition (SVD), High-Level Synthesis (HLS), Field Programmable Gate Array (FPGA).



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