FPGA Implementation of CNN for Handwritten Digit Recognition
Convolutional neural networks (CNN) have been used very successfully in the field of handwritten digit recognition. CNN is difficult to deploy on the embedded platform because of its large computation, complex structure and frequent memory access. In this paper, a manual hardware-level design (i.e., RTL) CNN reconfigurable IP core method is proposed to construct the FPGA basic unit of the CNN structure. Reconfigurable convolution, pooling and fully connected modules in the CNN structure are designed. By setting the parameters of the reconfigurable modules and connecting these modules end-toend, CNNs of different structure sizes can be quickly deployed. In the full connection module, using double cache technology can reduce the memory access operation of weight parameters and improve the calculation efficiency. In addition, this paper presents an FPGA implementation of CNN for handwritten digit recognition system. The system was built end-to-end using a reconfigurable IP core and was finally implemented on the lntel Cyclone10 FPGA hardware platform. Under the 150MHz clock, CNN only needs 0.0176 ms to recognize a handwritten digital picture, and the accuracy rate is 97.57%.
Convolutional neural networks, FPGA, RTL, Handwritten digit recognition