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Hardware Design of Approximate Matrix Multiplier based on FPGA in Verilog


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Abstract


Approximate computing has emerged as a new paradigm for the energy-efficient design of circuits and systems. It enables highly efficient hardware and software implementations by exploiting the inherent resilience of applications to in-exactness in their computations. In this work, hardware implementation of Matrix Multiplier based on approximate computing is modeled in VERILOG Hardware Description Language (HDL). The target device used for synthesis is xc7a100t-3csg324 in Xilinx. Simulations were performed in ISIM simulator and device utilization has been presented below.

KeyWords
approximate computing, matrix multiplier, Verilog, Field Programmable Array (FPGA), Look Up Tables (LUTs)



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