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Pipeline Stage Level Simulation Method for Self-Timed Data-Driven Processor on FPGA


3D Reconstruction in Canonical
Abstract


This paper describes an FPGA circuit simulation method for self-timed data-driven processor with ultra-low-power real-time multiprocessing capability preferable to IoT systems. To avoid the do-overs of circuit design, the processorÔ??s performance should be verified, in early design phase, against a given target. Although this processor is realized by an asynchronous circuit, most FPGA devices are oriented to clock-synchronized circuits and their CAD tools have no support for such high level verification. Conventionally, a gate-level simulation with actual circuit delay information is used as a substitute; however, it lacks flexibility and is becoming unavailable. Already, asynchronous circuit design methods for FPGA have been proposed, but they are primarily focused on circuit implementation and optimization. In this paper, we propose a high level simulation method to provide RTL simulation with stage-by-stage data transfer timing, and we show the proposed simulation can achieve the early design phase verification with a sufficient accuracy.

KeyWords
data-driven processor, self-timed pipeline, RTL simulation



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