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An Accurate and Quick ANN based System-Level Dynamic Power Estimation Model using LLVM IR Profiling for FPGA Designs


3D Reconstruction in Canonical
Abstract


The demand of early estimation of the power of semiconductor devices has risen due to technology scaling, growing complexity, and faster time to market. In this letter, we present the early power estimation model for FPGA based designs. We perform the profiling at C-level using LLVM IR and then training of the neural network from the profiling information to create the estimation model. The model accuracy is validated from the CHStone, MachSuite, and Rosetta-master benchmark applications. An insignificant relative error of 0.21% to 5.12% is observed for the analyzed benchmark designs with the exceptional increase in estimation speed by 87 times of magnitude as compared to the Xilinx Vivado Design Suite.

KeyWords
Design space exploration, Power estimation, Field programmable gate array (FPGA), Low-level virtual machine intermediate representation (LLVM IR), and Artificial neural network (ANN).



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