Efficient Reconfiguration Algorithm with Flexible Rerouting Schemes for Constructing 3D VLSI Sub-Arrays
In this paper, we investigated the technique for improving the reliability of 3D processor with faults by reconfiguring a 3D fault-free subarray utilizing as many non-faulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.
3D processor array, reconfiguration, fault tolerance, rerouting algorithm.