The Method Of Low Power, High Performance And Area Efficient Address Decoder Design For SRAM
In this paper a new method of design of CMOS decoder circuit was proposed. To minimize power consumption and increase the performance of the design the following design solutions have been combined: mixed-logic design method, combining transmission gate logic, dual-value logic pass-gate transistor and CMOS logic. Two new schematics are presented in the paper according which 2-4 decoders were designed. In the first solution a 14-FET based circuit was designed which can be used to minimize the area and power consumption of digital VLSI ICs. The 15-FET based circuit was also proposed to increase the performance of digital ICs while consuming more power than in 14-FET based solution. Using the above-mentioned cells, the following more complex digital decoders have been designed: inverting 14-FET based decoder, inverting 15-FET based decoder, noninverting and inverting 4-16 decoders. All the above proposed solutions have shown better performances, lower power consumptions and less required area of silicon compared to the ones currently used in digital designs. The proposed solutions have been analyzed by SPICE simulations and for 14- nm technology node shown better.
low-power design, VLSI; static random-access memory, SRAM, decoder, power consumption, high performance, high-speed, area impact, CMOS technology, PMOS, NMOS, transmission gate, pass-gate