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Bias-Dependent Variation in FinFET SRAM


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3D Reconstruction in Canonical
Abstract


In this brief, we investigate device variability in advanced fin field effect transistor (FinFET) static random access memory (SRAM) devices (12 and 7 nm) as a function of drain-to-source (Vds) bias. Draininduced barrier lowering (DIBL) and the variation in DIBL are found to exhibit a logarithmic dependence with drain bias in the advanced node FinFET devices. Correctly capturing the DIBL and device variation as a function of drain bias is required, as the SRAM operation voltage range is expanded. We show the improved hardware correlation in Vmin yield and the improved slow corner read performance when the Vds-dependent variation is considered.

KeyWords
Drain-induced barrier lowering (DIBL), fin field effect transistor (FinFET), local layout effects (LLE), scaling, static noise margin (SNM), static random access memory (SRAM), statistics, variation, Vmin, write margin (WRM), yield



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