A Low-Cost VLSI Architecture of the Bilateral Filter for Real-Time Image Denoising
In this paper, a low-cost hardware architecture of the bilateral lter for real-time image pro- cessing is proposed. Based on the techniques of distance-oriented grouping and hardware resource sharing, the usage of multipliers can decrease 48% as compared to the previous approach. Besides, an efcient quantization method is applied to reduce the size of required look up tables. The experimental results show that the proposed architecture is cost efcient while maintaining the same image quality, frame rate and working clock frequency.
Bilateral lter, image processing, noise reduction, real-time processing.