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Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing


Using Big Data Analytics to Cr

3D Reconstruction in Canonical
Abstract


Binary compressed sensing (BCS), in which signals of interest have binary values, finds applications in areas including fault detection and wireless sensor networks. In this article, a low-complexity VLSI architecture for BCS based on interval passing algorithm is proposed.Moreover, the algorithm is modified in order to reduce its complexity without significant loss in performance, and its corresponding VLSI architecture is proposed. Binary low-density parity check (LDPC) matrices based on finite geometry have been used as measurement matrices. The proposed VLSI architectures have been synthesized in both ASIC and field-programmable gate array (FPGA) platforms. The hardware consumption of the proposed designs is independent of sparsity values. Moreover, the proposed architectures offer high frequency of operation and low reconstruction time when compared to the state-of-the-art designs. Specifically, the 65-nm ASIC realization operates at a maximum frequency of 500 and 666.67 MHz and offer a reconstruction time of 6.3 and 4.7 ns, respectively, for a 64 ? 256 deterministic measurement matrix.

KeyWords
Binary compressed sensing (BCS), Euclidean geometry low-density parity check (EG-LDPC), interval passing algorithm (IPA), LDPC codes, VLSI



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