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A Novel Low Power Ternary Multiplier Design using CNFETs


3D Reconstruction in Canonical
Abstract


Carbon Nanotube Field Effect Transistors (CNFETs) are considered to be an ideal choice for implementation of Multi-valued logic circuits, as by using CNFETs multiple thresholds can be obtained by altering the dimensions of the carbon nanotube. Implementation of various CNFET based Ternary Arithmetic circuits like Adders and Multipliers is extensively researched upon. The existing design for a CNFET based Multiplier is based on the classicalWallace approach which uses 3:1 Multiplexers along with Unary operators of Ternary logic. In this paper, design of a novel low power Single-Trit Multiplier and a Three-Trit Multiplier is proposed which uses a 2:1 Multiplexer based design approach. This design shows considerable improvement in terms of power consumption. From the Hspice simulation results, it is noted that the proposed Single- Trit Multiplier design results in up to 99% reduction in Power consumption, 56% reduction in Delay and 99.8% reduction in Power-Delay Product (PDP) when compared to an existing Single- Trit Multiplier. Proposed Three-Trit Multiplier results in savings in power consumption up to 98.2% and 98.5% reduction in PDP when compared to Three-Trit Multiplier design in the existing literature.

KeyWords
CNFET, Single-Trit Multiplier, Three-Trit Multiplier, Ternary Logic, Low power.



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