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Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators


3D Reconstruction in Canonical
Abstract


On-chip digital low-dropout (LDO) regulators enable fast dynamic voltage scaling, reducing power consumption. Integrating these regulators into a highly resistive environment has complicated the design of power delivery systems. With the increasing sensitivity of complex integrated systems to power noise, effective approaches to distribute on-chip LDOs are needed due to the limited metal resources. In this article, a methodology is proposed to distribute the pass gates of a system of onchip digital LDOs. The distribution of the pass gates considers the location of the load currents to reduce voltage variations across the power grid. The proposed pass gate distribution topology reduces the maximum voltage variations across the grid, on average, by two to three times under nonuniform load distributions.

KeyWords
Digital low-dropout (LDO), on-chip voltage regulator, parasitic resistance, power delivery noise.



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