Alternative Reduced Hardware MASH1-1-1 Digital Delta Sigma Architecture
This paper presents a modified structure of the digital accumulator, which provides the maximum cycle length of (2n + 1). By using this structure Multistage noise shaping (MASH1-1-1) digital delta-sigma modulator (DDSM) is developed which yields the maximum cycle length of (2" + l ) 3 for most of the applied inputs, where n is the word length of the accumulator. The proposed MASH1-1-1 architecture has been compared with the various existing MASH1-1-1 architectures and shows a better performance in terms of noise shaping, input range and hardware consumption. Above performances have been shown by simulations, verified mathematically and digital gate counts.
Digital delta-sigma modulator (DDSM), Multistage noise shaping (MASH)