Algorithm and Architecture of an Efficient MIMO Detector With Cross-Level Parallel Tree-Search
The metric-first-based multiple-input‚??multipleoutput (MIMO) detection algorithm can achieve optimal performance with large stack size, which leads to huge memory consumption and extremely high-sorting complexity. This article presents the algorithm and architecture of a soft-input‚??softoutput metric-first MIMO detection. The proposed algorithm divides the global stack into multiple local stacks for each nonleaf of the tree. Furthermore, each level of the search tree is performed in parallel to improve the throughput and hardware efficiency. In the proposed algorithm, the hybrid enumeration strategy significantly reduces the computational complexity by avoiding the full enumeration and sorting. The simulation results show the novel algorithm can achieve good performance with lower complexity than other metric-first methods. The proposed detector has been designed for a 4 √? 4 64-QAM MIMO system and implemented in SMIC 65-nm CMOS technology. The detector can operate at 333-MHz clock frequency and achieve a maximum throughput of 799.2 Mb/s at a 17.3-dB signal-to-noise ratio with area equivalent 242 kg and power consumption of 102.3 mW, and the hardware efficiency is 3.3 Mb/s/kg. Compared with other detectors based on the metric-first algorithm, this article has an obvious advantage in terms of throughput and hardware efficiency.
Metric first, soft-input‚??soft-output (SISO) detection, tree-search, VLSI architecture