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NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization


Using Big Data Analytics to Cr

3D Reconstruction in Canonical
Abstract


Use of standard cells in the very-large-scale integration (VLSI) design enables very short time to market even for complex microprocessors. Thus, most VLSI layouts are designed using standard cells. In this paper, we propose a new design methodology, namely NP-Separate, to reduce the power consumption and area and increase the performance of a VLSI layout more effectively than the standard-cell-based design methodology. NP-Separate uses N cells and P cells composed of NFETs and PFETs only, respectively, thereby providing a higher degree of flexibility than using standard cells. Our simulation results for several benchmark circuits show that NP-Separate reduces the layout area by 9%, power consumption by 10%, power-delay product by 18%, and energy-delay product by 26% on average while satisfying given timing constraints compared to standard-cell-based designs.

KeyWords
Physical layout design, VLSI, standard cells



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