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VLSI Architecture for High Performance Wallace Tree Encoder


3D Reconstruction in Canonical
Abstract


In the research, the VLSI architecture design for Wallace tree encoder with modified full adder is proposed. In analog to digital conversion process, Wallace tree encoder is utilized in the process of converting the thermometer code to binary. This can be termed to be a high speed application and a flash type of flash ADC, which is a resistor ladder, encoder and comparator circuit. A suitable encoder is required for getting binary code from comparator output. Reducing energy of the encoder is a vital concern whereas designing the minimal power flash form ADC. Wallace tree encoders diminishes the mistake due to the availability of zeroes in the sequence of the once presence to the series of zeroes in a comparator output, but it consumes more power. Hence in the proposed work, a low power Wallace tree encoder is designed using pass transistor logic (PTL) full adder. The proposed design dissipates only 74.15nW power and delay also reduced to 0.0495ns. The circuit is designed using CADENCE 5.1.0 EDA equipped and simulated with the application of spectre virtuoso.

KeyWords
Wallace Tree encoder, pass transistor logic,low power.



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