VLSI Architectures for ORVD Trellis based MIMO Detection
A novel architecture structuring MIMO Detection with a Trellis search is presented. Therefore, several optimizations are explored reducing complexity and increasing efficiency. Implementing orthogonal real-value decomposition outperforms the basic implementation by a factor of 2.7 in terms of area throughput efficiency, preserving a comparable communication performance. This concept also allows suitable scaling towards higher modulation orders and also offers a potential for further architectural scaling. Optimizations are applied on algorithmic and architectural level to reduce complexity and increase efficiency. A design space exploration of the sorting subtask is also presented. It achieves the IEEE 802.11n standardÔ??s peak data rate, even for two detector decoder iterations (2 ├? 720 Mbit/s).
Very large scale integration (VLSI), MIMO Detection, Computer architecture, Sorting implementations