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A High Speed VLSI Architecture for Scaleable ATM Switches


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Abstract


This paper presents a prototype of a VLSI chip to be used as a building block for an efficiently scaleable ATM switch with a link speed of 622.2 Mbis. The chip is a 4x4 shared multibuffer ATM switch based on the distributing banyan architecture. It is efficient in storage space like a shared memory switch and scaleable in size like a space division switch. Since the architecture is self-routing, the chip contains all necessary routing control. Special high speed and low power circuitry is used. The chip is implemented in 1.0 micron static CMOS and measures only 25 nun2 in area.

KeyWords
ATM CMOS



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