A Circuit Technique for Leakage Power reduction in CMOS VLSI Circuits
Scaling of CMOS technology improved the speed
nevertheless the leakage currents are leftover as an adverse
effect. The problem has taken a serious turn as the scaling
extends into ultra-deep-submicron (UDSM) region. These
unsolicited leakage currents should be minimized for the smooth
functioning of the circuit. Designing of such leakage free
nanoscale CMOS circuits turns to be a challenging task. In this
work, we address the issue of leakage power that arises with the
device channel length scaling to sub-100nm. We present a circuit
technique to mitigate the leakage currents of MOSFET through
controlling the voltage at the source terminal of the MOSFET.
CMOS inverter designed using the proposed technique results in
98% and 30% improvement in static and total power dissipation
respectively compared with its conventional design. The
simulation results of NAND and NOR gates designed using the
same technique indicates 15.89% and 18.83% improvement in
the total power compared with their corresponding conventional
designs. 11-stage CMOS ring oscillator designed using the
proposed technique is analyzed, and corresponding simulation
results are reported. Comparison of the proposed circuits in
terms of power dissipation and delay with two existing techniques
is presented. The circuits designed using the proposed technique
results in good Power-Delay Product (PDP)
KeyWords
CMOS UDSM leakage power CMOS inverter
low power dissipation
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